1. Technical Field
This invention generally relates to computer memory systems and memory coherency, and more specifically relates to a circuit and method for handling a pipeline bit across a bus bridge.
2. Background Art
Access response from computer main memory is typically much slower than processor cycle times. Efficient mechanisms to bridge this gap between memory and processor cycle times are central to achieving high performance in computer systems. The conventional approach to bridging the gap between memory access time and processor cycle time has been to introduce a high-speed memory buffer, commonly known as a cache, between the processor and main memory. The main purpose of a cache memory is to provide fast access time while reducing bus and memory traffic. Some systems include two or more intermediate cache levels.
One of the problems that arise in computer systems that include a plurality of caching agents and a shared data cache memory hierarchy is the problem of cache coherency. Cache coherency refers to the problem wherein—due to the use of multiple, or multi-level, cache memories—data may be stored in more than one location in memory. By way of example, if a microprocessor is the only device in a computer system which operates on data stored in memory, and the cache is situated between the CPU and memory, there is little risk in the CPU using stale data. However, if other agents in the system share storage locations in the memory hierarchy, this creates an opportunity for copies of data to be inconsistent, or for other agents to read stale copies.
Cache coherency is especially problematic in computer systems which employ multiple processors as well as other caching agents (e.g., input/output (I/O) devices). A program running on multiple processors requires that copies of the same data be located in several cache memories. Thus, the overall performance of the computer system depends upon the ability to share data in a coherent manner.
Some processor bus specifications define a pipeline bit (P-bit) that assists the processor in maintaining data coherency. In this type of bus domain, the system may pipeline transactions if the P-Bit is asserted (P=1). If the P-Bit is not asserted (P=0), the system must not pipeline other P=0 transactions. Thus, using this P-Bit, a master can ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. In this type of bus system, there is typically an address concentrator that issues a snoop request after receiving a first P=0 command to determine if any other cache is holding data corresponding to the P=0 command. The address concentrator would also hold any subsequent P=0 commands until the first command is completed. Thus the address concentrator typically spaces snoop requests to maintain separation between P=0 commands
In a system where there is a bus bridge between a first bus that uses a P=0 for a pipeline bit, and a second bus that uses a P-bit for a priority bit or does not use a pipeline bit, there is a need for a way to accommodate for the difference in the P=0 bit commands.